The present invention relates to a data alignment circuit; and, more particularly, to a technology for aligning serial input data in parallel.
In order to process data between various semiconductor chips or within these chips at a high speed, the data is generally communicated between or within them by a serial interface. Then, a receiver in each chip receives the serial data and uses the same after internally aligning them in parallel. For example, a 4-bit prefetch, an 8-bit prefetch specified and so on specified in the specification of a semiconductor memory device (DRAM) define what number of data is internally made in parallel.
In general, four clocks with different phases are used for aligning serial input data into parallel data of more than 4 bits, wherein the four clocks are generated by a PLL (Phase Locked Loop). The reason of using the four clocks with different phases is to latch the serial data and parallelize the same, respectively. FIG. 1 shows that four clocks clk<0>, clk<1>, clk<2>, and clk<3> with different phases latch serial input data, respectively.
FIG. 2 is a configuration diagram illustrating a conventional circuit for data alignment.
The conventional circuit for data alignment takes serial input data from a buffer 210 and latches the data by clocks clk000, clk090, clk180, and clk270 with different phases to catch the same. Then, the timing of the data caught by each of latches 221, 222, 223, and 224 is adjusted by a timing adjustor 230 to output parallel data.
As shown in the drawing, for example, when data 0, 1, 2, and 3 are inputted in series, the data are latched by each of the latches 221, 222, 223, and 224 by using clocks clk000, clk090, clk180, and clk270 with different phases and then the timing of the latched data is adjusted, thereby outputting the data 0, 1, 2, and 3 in parallel at the same time.
At this time, the four clocks clk000, clk090, clk180, and clk270 with different phases are generally provided from a PLL.
As described above, the convention circuit for data alignment employs the four clocks with different phases so as to parallelize the serial input data in the ratio of 1:4. This 1:4 parallelization has the meaning of aligning the four data being inputted in series and outputting them in parallel (that is, of inputting data through one terminal and outputting them through four terminals). In this case, the frequency of the clocks with different phases used therein is lower than that of the data. Typically, as a clock has a lower frequency, the characteristics of jitter become deteriorated. Therefore, the use of the conventional method causes damage to the characteristics of jitter.
In addition, due to coupling noise and the like between lines in the process of delivering the four clocks with different phases generated by the PLL from the PLL to the circuit for data alignment, there is a problem that the skew between the clocks becomes bad.
In particular, in a GDDR memory device using the circuit for data alignment, 32 or more data are often aligned in parallel. In this case, however, since the number of clocks used and the number of lines for delivery thereof are large, the jitter and skew problems becomes more serious.